SystemVerilog Cross Coverage - Verification Guide
Cross coverage is specified using the cross construct. Expressions cannot be used directly in a cross; a coverage point must be explicitly defined first. Cross coverage by cover_point name bit [3:0] a, b; covergroup cg @(posedge clk); c1: coverpoint a; c2: coverpoint b; c1Xc2: cross c1,c2; endgroup : cg Cross coverage by the variable name
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